Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process

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Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process 08:47:45 Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm... -- SAN JOSE, Calif., Sept. Cadence Logo Cadence Logo ><- stripped tags -> SAN JOSE, Calif. , Sept. Cadence Design Systems, Inc. (NASDAQ: [[UEdFZ2NtVnNQVndpYm05bWIyeHNiM2RjSWlCb2NtVm1QU2RvZEhSd09pOHZjM1IxWkdsdkxUVXVabWx1WVc1amFXRnNZMjl1ZEdWdWRDNWpiMjB2Y0hKdVpYZHpQMUJoWjJVOVVYVnZkR1VtVkdsamEyVnlQVU5FVGxNbklISmxiRDBuYm05bWIyeHNiM2NuSUhSaGNtZGxkRDBuWDJKc1lXNXJKeUIwYVhSc1pUMG5RMFJPVXljZ2IyNWpiR2xqYXowbmJHbHVhMDl1UTJ4cFkyc29kR2hwY3lrbklISmxiRDBuYm05bWIyeHNiM2NuUGtORVRsTThMMkUrfA==]]) today announced that its digital, custom/analog and signoff tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve V1.0 completion by Q4 2015. The certification enables systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high-end servers. The Cadence® custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. The Cadence tools in the flow include: Innovus™ Implementation System: The solution incorporates a massively parallel architecture that enables increased capacity and a reduced turnaround time. It supports all of the TSMC 10nm design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization. Quantus™ QRC Extraction Solution: This signoff extraction solution supports both cell-level and transistor-level extractions during design implementation and signoff using one unified foundry-certified techfile. It meets TSMC accuracy requirements for all 10nm modeling features, including multi-patterning, multi-coloring, and built-in 3D extraction capability, and produces the smallest netlist to expedite simulation runtimes. Tempus™ Timing Signoff Solution: This solution offers integrated, advanced process delay calculation and static timing analysis (STA) that meets TSMC's rigorous accuracy standards for the 10nm process. Massive parallelism in computation coupled with "in-design" signoff engineering change orders (ECOs) in the Innovus Implementation System rapidly address signoff closure to minimize ECO iteration time. Voltus™ IC Power Integrity Solution: This SoC power signoff tool is certified for its accuracy in supporting comprehensive electromigration and IR-drop (EM/IR) design rules and requirements for the TSMC 10nm process. Together with other Cadence products in the flow, Voltus IC Power Integrity Solution provides a gate-level total power integrity analysis and optimization solution that helps customers to achieve the best power, performance and area (PPA), along with a fast path to design closure. Voltus-Fi Custom Power Integrity Solution: This SPICE-level accurate, transistor-level tool is used to analyze and signoff analog, memory and custom digital IP blocks, and create accurate macro models that represent the power grid view of the IP blocks during the SoC power signoff run with Voltus IC Power Integrity Solution. It is certified by TSMC for its accuracy in supporting comprehensive EM/IR design rules and requirements for the 10nm process down to the transistor device level. Virtuoso® custom IC advanced-node platform : This custom design platform provides the innovative "in-design to signoff" flows, integrating signoff-quality electrical and physical design checking that is highly correlated to the Cadence TSMC-certified signoff platforms. Customers experience fewer iterations in all design verification categories, which translates directly into increased designer productivity. Spectre® simulation platform: Spectre Circuit Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre eXtensive Partitioning Simulator (XPS) deliver fast and accurate circuit simulation with full support for 10nm device models with self-heating and reliability effects. Physical Verification System: PVS includes advanced technologies such as pattern matching, interactive DRC and in-design signoff using the Virtuoso custom IC platform and the Innovus Implementation System to significantly reduce iterations and achieve faster design closure. Litho Electrical Analyzer: The TSMC API integration with Litho Electrical Analyzer allows layout-dependent effects- (LDE-) aware resimulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate 10nm analog design convergence in the Virtuoso custom IC advanced-node platform. For more information on the Cadence tools, please visit [[UEdFZ2NtVnNQVndpYm05bWIyeHNiM2RjSWlCdmJtTnNhV05yUFNkc2FXNXJUMjVEYkdsamF5aDBhR2x6S1NjZ2FISmxaajFjSW1oMGRIQTZMeTkzZDNjdVkyRmtaVzVqWlM1amIyMHZjSEp2WkhWamRITXZVR0ZuWlhNdllXeHNYM0J5YjJSMVkzUnpMbUZ6Y0hoY0lpQnlaV3c5WENKdWIyWnZiR3h2ZDF3aUlIUmhjbWRsZEQxY0lsOWliR0Z1YTF3aVBtaDBkSEE2THk5M2QzY3VZMkZrWlc1alpTNWpiMjB2Y0hKdlpIVmpkSE12VUdGblpYTXZZV3hzWDNCeWIyUjFZM1J6TG1GemNIZzhMMkUrfA==]]. Cadence and TSMC also worked closely on the delivery of a 10nm custom design reference flow (CDRF). The CDRF includes the following: TSMC API integration that speeds up statistical simulation flows New layout automation capabilities for better managing LDE Robust capabilities for designing correct-by-construction FinFET arrays to avoid density gradient effects New patterning methods and functionality for handling today's sophisticated multi-patterning design styles Support for extracting and analyzing real-time parasitics and EM violations during design implementation "Through our deep collaboration with TSMC, we continue to focus heavily on advancing new innovations in the systems and semiconductor industries, enabling customers to confidently deliver advanced-node designs to the market," said Dr. Chi-Ping Hsu , senior vice president and chief strategy officer for EDA at Cadence. "We are now actively working with customers on 10nm designs and seeing great successes that ensure our customers can stay in front of the competition." "We've continued to deepen our collaboration with Cadence to certify the Cadence toolset on the TSMC 10nm technology," said Suk Lee , TSMC senior director, Design Infrastructure Marketing Division. "The reference flows in both digital and custom design can help customers reduce iterations and improve predictability while bringing their products to the market." In related news, please see the Cadence press release titled, "TSMC Certifies Cadence Innovus Implementation System on 10nm FinFET Process," at [[UEdFZ2NtVnNQVndpYm05bWIyeHNiM2RjSWlCdmJtTnNhV05yUFNkc2FXNXJUMjVEYkdsamF5aDBhR2x6S1NjZ2FISmxaajFjSW1oMGRIQTZMeTkzZDNjdVkyRmtaVzVqWlM1amIyMHZZMkZrWlc1alpTOXVaWGR6Y205dmJTOXdjbVZ6YzE5eVpXeGxZWE5sY3k5UVlXZGxjeTl3Y2k1aGMzQjRQM2h0YkQwd09URTJNVFZmZEhOdFkybHVibTkyZFhOY0lpQnlaV3c5WENKdWIyWnZiR3h2ZDF3aUlIUmhjbWRsZEQxY0lsOWliR0Z1YTF3aVBtaDBkSEE2THk5M2QzY3VZMkZrWlc1alpTNWpiMjB2WTJGa1pXNWpaUzl1WlhkemNtOXZiUzl3Y21WemMxOXlaV3hsWVhObGN5OVFZV2RsY3k5d2NpNWhjM0I0UDNodGJEMHdPVEUyTVRWZmRITnRZMmx1Ym05MmRYTThMMkUrfA==]]. About Cadence Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif. , with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at [[UEdFZ2NtVnNQVndpYm05bWIyeHNiM2RjSWlCdmJtTnNhV05yUFNkc2FXNXJUMjVEYkdsamF5aDBhR2x6S1NjZ2FISmxaajFjSW1oMGRIQTZMeTkzZDNjdVkyRmtaVzVqWlM1amIyMHZkWE12Y0dGblpYTXZaR1ZtWVhWc2RDNWhjM0I0UDBOTlVEMXdjakE1TVRZeE5WOTBjMjFqTVRCdWJVWkdZMlZ5ZEZ3aUlISmxiRDFjSW01dlptOXNiRzkzWENJZ2RHRnlaMlYwUFZ3aVgySnNZVzVyWENJK2QzZDNMbU5oWkdWdVkyVXVZMjl0UEM5aFBnPT18]]. This news release contains certain forward-looking statements, including expectations for the timing and results of certification efforts and collaboration with TSMC, that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. This news release also contains forward-looking statements attributed to third parties, which reflect their expectations as of the date of issuance. Risks that may cause these forward-looking statements to be inaccurate include among others: Cadence's technology and products described in this press release may not perform as expected, Cadence's certification and collaboration efforts may be altered or delayed, or the other risks detailed from time-to-time in our Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this press release. © 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Spectre and Virtuoso are registered trademarks and Innovus, Quantus, Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners. For more information, please contact:Cadence Newsroom